• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention provides a method for forming a contact hole in a semiconductor device that can effectively fill a conductive film in a small contact hole and prevent generation of steps in the sidewalls of the contact hole, wherein the interlayer insulating film is selectively etched before forming the contact hole. The polysilicon film spacer is formed on the sidewalls of the interlayer insulating film, and then the interlayer insulating film is formed again and selectively etched to form a contact hole, and the BOE solution treatment is performed for a predetermined time to increase the size of the contact hole. The margin of the contact hole forming process can be secured.
    公开号:KR19990046866A
    申请号:KR1019970065019
    申请日:1997-12-01
    公开日:1999-07-05
    发明作者:인성욱
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Method for forming contact hole in semiconductor device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole exposing a surface of a semiconductor substrate between adjacent gate electrodes at predetermined intervals.
    In order to obtain a small chip size in accordance with high integration of semiconductor devices, a small contact hole is used. In this case, an aspect ratio increases, making it difficult to embed a metal film.
    In addition, after forming a contact hole in an interlayer insulating film composed of a BPSG (borophosphorsilicate) film and a thermal oxide film, a BOE (buffered oxide etchant) solution treatment is performed to remove a natural oxide film that increases contact resistance. Due to the difference in the etching rate of the thermal oxide film with respect to the BOE solution, a step occurs in the contact hole sidewall.
    Therefore, since the barrier metal film and the Ti film are not deposited along the contact hole sidewalls, subsequent metal films are not effectively buried in the contact hole, thereby failing to obtain stable device characteristics.
    The present invention devised to solve the above problems is to provide a method for forming a contact hole in a semiconductor device capable of effectively embedding a conductive film in a contact hole having a large aspect ratio and a small size.
    1A to 1I are sectional views of a contact hole forming process of a semiconductor device according to an embodiment of the present invention.
    * Description of the main parts of the drawing
    10: semiconductor substrate 11: gate insulating film
    12: gate electrode 13: oxide film spacer
    14, 15, 16, 17, 18, 21, 22: interlayer insulating film 19, 23: photoresist pattern
    20: undoped polysilicon film spacer
    24: opening of contact hole 25: contact hole
    26: barrier metal film 27: metal film
    According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method comprising: forming a first interlayer insulating film on the semiconductor substrate; Selectively removing the first interlayer insulating film to form adjacent first interlayer insulating film patterns at predetermined intervals; Forming a non-doped polysilicon layer to cover the entire structure formed on the semiconductor substrate and etching the entire surface to form a polysilicon layer spacer on sidewalls of the first interlayer insulating layer pattern; Forming a second interlayer insulating film covering the entire structure formed on the semiconductor substrate; Selectively removing the second interlayer insulating film to form a contact hole exposing a surface of the semiconductor substrate; And wet etching the second interlayer insulating layer exposed on the sidewalls of the contact hole to widen the width of the contact hole.
    Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
    In the method of forming a contact hole in a semiconductor device according to an embodiment of the present invention, as shown in FIG. 1A, a gate insulating film 11, a gate electrode 12, an oxide film spacer 13, and the like are formed on a semiconductor substrate 10. A predetermined lower layer is formed. In this case, the gate electrode is a gate electrode of two neighboring transistors at predetermined intervals.
    Subsequently, first, second, third, fourth, and fifth interlayer insulating films are formed in sequence. The first, third and fifth interlayer insulating films 14, 16 and 18 are formed of TEOS (tetra ethly orthosilicate) oxide films, and the second and fourth interlayer insulating films 15 and 17 are formed of BPSG films. . In addition, the first, third, and fifth interlayer insulating films 14, 16, and 18 are oxide films (IPOs) for insulating the polysilicon film.
    Next, as shown in FIG. 1B, a predetermined photoresist pattern 19 is formed on the fifth interlayer insulating layer 18 as an etch stop layer.
    Next, as illustrated in FIG. 1C, the fifth, fourth, third, second, and first interlayer insulating films 18, 17, 16, 15, and 14 may be selectively formed using the photoresist pattern 19 as an etch mask. Etching is performed to expose the surface of the semiconductor substrate between the neighboring gate electrodes and simultaneously stack the gate electrodes 12 and the first, second, third, fourth, and fifth interlayer insulating films 14, 15, and 16. , 17, 18) to form a structure. Next, the photoresist pattern 19 is removed.
    Next, as shown in FIG. 1D, an undoped polysilicon film is formed, and the surface is etched to the first, second, third, fourth, and fifth interlayer insulating films 14, 15, 16, 17, and 18. An undoped polysilicon film spacer 20 is formed on the sidewall of the structure.
    Next, as shown in Fig. 1E, sixth and seventh interlayer insulating films 21 and 22 are formed of an oxide film and a BPSG film.
    Next, as shown in FIG. 1F, the sixth interlayer insulating layer 21 and the seventh interlayer insulating layer 22 are selectively etched to form contact holes connected to the surface of the semiconductor substrate between two neighboring gate electrodes. The photosensitive film pattern 23 is formed. Subsequently, the photoresist pattern 23 is wet-etched with an etching mask to remove a part of the seventh interlayer insulating layer 22 formed of the BPSG film to form the opening 24 of the contact hole. In this case, the opening 24 of the contact hole is formed larger than the size of the contact hole due to the wet etching. That is, not only the seventh interlayer insulating layer 22 exposed between the photoresist pattern 23 during the wet etching process, but also a part of the seventh interlayer insulating layer 22 formed under the photoresist pattern 23 is removed.
    Next, as shown in FIG. 1G, dry etching is performed on the photoresist pattern 23 using an etching mask to form a contact hole 25 exposing the surface of the semiconductor substrate between two neighboring gate electrodes. Next, the photoresist pattern 23 is removed.
    Next, as shown in FIG. 1H, a BOE solution treatment for removing a native oxide film or the like existing in the contact hole is performed. At this time, the BOE solution treatment is performed for a sufficient time to obtain a contact hole width b wider than the contact hole width a (see FIG. 1G) formed in the dry etching process. In this case, the undoped polysilicon layer spacer 20 may be exposed by the BOE solution treatment. Subsequently, a barrier metal layer 26 and a metal layer 27 are formed in the contact hole 25 and on the seventh interlayer insulating layer 22.
    Next, as shown in FIG. 1I, the metal film 27 and the barrier metal film 26 are patterned to form metal wires connected to the surface of the semiconductor substrate 10 through the contact holes 25. do.
    The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
    According to the present invention as described above, after forming the contact hole by etching the interlayer insulating film, the contact hole formed in the previous step can be expanded by performing the BOE solution treatment for a sufficient time before forming the barrier metal film. A contact hole forming process margin of can be secured.
    In addition, by forming an undoped polysilicon film spacer formed prior to forming the contact hole, it is possible to prevent the occurrence of a step on the sidewall of the contact hole by preventing the interlayer insulating film having a plurality of layers having different etching rates from being exposed to the BOE solution. Therefore, it is possible to effectively deposit a metal film in the contact hole.
    In addition, the undoped polysilicon film formed on the outer side of the contact hole may effectively insulate between neighboring conductive films to secure a short margin.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] Forming a first interlayer insulating film on the semiconductor substrate;
    Selectively removing the first interlayer insulating film to form adjacent first interlayer insulating film patterns at predetermined intervals;
    Forming a non-doped polysilicon layer to cover the entire structure formed on the semiconductor substrate and etching the entire surface to form a polysilicon layer spacer on sidewalls of the first interlayer insulating layer pattern;
    Forming a second interlayer insulating film covering the entire structure formed on the semiconductor substrate;
    Selectively removing the second interlayer insulating film to form a contact hole exposing a surface of the semiconductor substrate; And
    And wet-etching the second interlayer insulating layer exposed on the sidewalls of the contact hole to widen the width of the contact hole.
    [2" claim-type="Currently amended] The method of claim 1,
    Forming the contact hole,
    Forming an etch stop layer on the second interlayer insulating layer;
    Removing a portion of the second interlayer insulating layer exposed between the etch stop layers by performing wet etching, and forming an undercut under the etch stop layer;
    Removing the etch stop layer; And
    A method of forming a contact hole in a semiconductor device comprising the step of performing a dry etching.
    [3" claim-type="Currently amended] The method according to claim 1 or 2,
    And forming the first interlayer insulating film in a stacked structure including a BPSG film and a TEOS oxide film.
    [4" claim-type="Currently amended] The method according to claim 1 or 2,
    And forming the second interlayer dielectric film as a BPSG film.
    [5" claim-type="Currently amended] The method of claim 4, wherein
    The method of claim 1, wherein the wet etching is performed using a BOE solution.
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    同族专利:
    公开号 | 公开日
    KR100436063B1|2004-07-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-12-01|Application filed by 김영환, 현대전자산업 주식회사
    1997-12-01|Priority to KR1019970065019A
    1999-07-05|Publication of KR19990046866A
    2004-07-16|Application granted
    2004-07-16|Publication of KR100436063B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970065019A|KR100436063B1|1997-12-01|1997-12-01|Method of forming contact hole of semiconductor device using spacer made of undoped polysilicon layer|
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